FIG. 1 shows an example semiconductor device 102 that is a memory device such as a DRAM (dynamic random access memory). The DRAM 102 includes an array of memory cells 104. Each memory cell such as an example memory cell 106 is coupled to a corresponding word line 108 and a corresponding bit line 110. Typically, a row of memory cells are coupled to a same word line, and a column of memory cells are coupled to a same bit line.
The DRAM 102 also includes an address input buffer 112 that receives an address corresponding to a memory cell to be accessed within the array 104. A column address (CA) is decoded by a column decoder 114 for activating a bit line corresponding to such a memory cell to be accessed. A row address (RA) is decoded by a row decoder 116 for activating a word line corresponding to such a memory cell to be accessed.
A sense amplifier 118 amplifies a signal from a read memory cell before such data is output via an I/O buffer 120 as output data DQ. When the memory device 102 is a synchronous device, a synchronized clock signal CLKDQ is generated by a delay locked loop (DLL) 122 (or a phase locked loop (PLL)) from an external clock signal CLK. The synchronized clock signal CLKDQ is used by the I/O buffer 120 for timing of the output data DQ.
A command decoder 124 decodes external command signals for generating internal command signals such as “active”, “write”, “read”, “refresh”, and “MRS (mode register set)” commands for controlling operations within the array of memory cells 104. Such commands with corresponding operations within the array of memory cells 104 are known to one of ordinary skill in the art.
The above described components of the memory device 102 derive power from various voltage sources. The memory device 102 uses both external voltages provided from external voltage sources and internal voltages generated internally by an internal voltage generator 126.
Referring to FIGS. 1 and 2, each of such voltage sources has a respective decoupling capacitor coupled between a respective pair of high and low nodes. A first decoupling capacitor 132 is coupled between high and low nodes VDD and VSS of a first voltage source. Such a voltage source is typically used for a peripheral circuit providing data paths from the array 104.
A second decoupling capacitor 134 is coupled between high and low nodes VDDQ and VSSQ of a second voltage source. Such a voltage source is typically used within the I/O buffer 120 for charging/discharging of the outputs DQ. A third decoupling capacitor 136 is coupled between high and low nodes VDDA and VSSA of a third voltage source. Such a voltage source is typically used within the array of memory cells 104 and for the sense amplifier 118.
A fourth decoupling capacitor 138 is coupled between high and low nodes VDDL and VSSL of a fourth voltage source. Such a voltage source is typically used by the delay locked loop 122. Such decoupling capacitors 132, 134, 136, and 138 are formed for the external voltage sources VDD/VSS, VDDQ/VSSQ, VDDA/VSSA, and VDDL/VSSL.
A fifth decoupling capacitor 140 is coupled between high and low nodes VINT and VSS of a fifth voltage source. Such voltages are internally generated by the voltage generator 126 for the peripheral circuit outside of the array of memory cells 104. A sixth decoupling capacitor 142 is coupled between high and low nodes VINTA and VSSA of a sixth voltage source. Such voltages are internally generated by the voltage generator 126 to be used within the array of memory cells 104.
A seventh decoupling capacitor 144 is coupled between high and low nodes VPP and VSS of a seventh voltage source. Such voltages are internally generated by the voltage generator 126 as a word line boosting voltage or as a gate voltage for isolation and equalization units within the array of memory cells 104.
An eighth decoupling capacitor 146 is coupled between high and low nodes VBB and VSS of an eighth voltage source. Such voltages are internally generated by the voltage generator 126 as a back bias for a cell access transistor or as a word line pre-charge voltage within the array of memory cells 104. Such decoupling capacitors 140, 142, 144, and 146 are formed for the internally generated voltage sources VINT/VSS, VINTA/VSSA, VPP/VSS, and VBB/VSS.
The decoupling capacitors 132, 134, 136, 138, 140, 142, 144, and 146 are fabricated as part of the integrated circuit of the semiconductor device 102. The capacitance of each of such decoupling capacitors is desired to be large for more stable operation of the semiconductor device.
For example, FIG. 3 shows an example I/O buffer 120 having a pull-up transistor MP1 and a pull-down transistor MN1 coupled between the nodes VDDQ and VSSQ. The sense amplifier 118 provides control signals DATA_UP and DATA_DN to turn on one of the transistors MP1 and MN1. FIG. 4 shows a timing diagram of operation of the I/O buffer 120 of FIG. 3.
Referring to FIGS. 3 and 4, during a charging time period 152, the pull-up transistor MP1 is turned on to charge the output DQ to the high voltage VDDQ. Thereafter during a discharging time period 154, the pull-down transistor MN1 is turned on to discharge the output DQ to the low voltage VSSQ. During such charging/discharging time periods 152 and 154, the voltage levels at the two nodes VDDQ and VSSQ deviate from the intended levels. Because of such a deviation, the DQ signal has undesired jitters during the charging/discharging time periods 152 and 154.
The undesired deviations of VDDQ and VSSQ and the undesired jitters of the DQ signal during the charging/discharging time periods 152 and 154 are minimized with higher capacitance of the decoupling capacitor 134 coupled between VDDQ and VSSQ. Similarly, the capacitance of each of the decoupling capacitors 132, 134, 136, 138, 140, 142, 144, and 146 is desired to be large for more stable operation of the semiconductor device 102. However, larger capacitance for such decoupling capacitors undesirably increases the area of the integrated circuit of the semiconductor device 102.
Referring to FIG. 5, Korean Patent Application No. P2000-0037234 discloses a capacitance control section 30 for coupling a control capacitor 10 to one of a first voltage source Vext and a second voltage source Vdd. The voltage levels Vext and Vdd are with respect to a same ground node 162 in FIG. 5.
Further referring to FIG. 5, the control section 30 includes a first PMOSFET PM2 coupled between Vext and the control capacitor 10 and includes a second PMOSFET PM3 coupled between Vdd and the control capacitor 10. The first PMOSFET PM2 has a gate coupled to a SEL (select) signal, and the second PMOSFET PM3 has a gate coupled to the SEL signal through an inverter IV5.
FIG. 6 shows a timing diagram for operation of the control section 30 of FIG. 5. During a first time period 164 and a third time period 168, the SEL signal is a logical high state for turning on the second PMOSFET PM3 to couple the control capacitor 10 to Vdd for a pre-charge operation of a memory device. During a second time period 166, the SEL signal is a logical low state for turning on the first PMOSFET PM2 to couple the control capacitor 10 to Vext for a read operation of the memory device.
Unfortunately, in the prior art of FIGS. 5 and 6, the voltage sources Vext and Vdd are with respect to a same ground node 162, resulting in higher noise. In addition in the prior art of FIGS. 5 and 6, distribution of capacitance of the control capacitor 10 is varied among voltages Vext and Vdd during operation of the memory device depending on the operation mode of the memory device. However, such distribution may not necessarily result in best performance of the memory device.
Thus, an alternative mechanism for distributing capacitance of a shared capacitor is desired for lower noise and higher performance of a semiconductor device.